False locking occurs when a phase locked loop locks to a frequency other than that of a data stream from which a clock signal is to be recovered. False locking to harmonics (e.g. half or double) of the data stream baud rate sometimes occurs. False locking can also occur at other frequencies which are closer to the baud rate of the data stream. This occurs because a standard phase detector used for recovery of clock from a data stream may not drive a phase locked loop to lock if the phase locked loop voltage controlled oscillator (VCO) and the data stream differ in frequency by more than a small amount. This difference is typically much less than the total frequency range of the VCO. This is normally the case with VCOs that are implemented in very large integrated circuits (VLSI) because such VCOs must have a wide frequency range to ensure that across variations in process, voltage and temperature, the VCO range always encompasses the frequency of data streams from which the clock frequency and phase is to be recovered. A discussion of "false locking" can be found in the paper "The Applications of Linear Servo Theory to the Design of AGC Loops", by W. K Victor in Proceedings of the IRE, Vol 48, February 1960.
Existing systems typically use one of two approaches to avoid false locking. The first approach is to tune or trim the VCO such that its total frequency range is limited and is centered about the frequency of the data stream to be recovered. If the VCO is restricted sufficiently, this ensures that the phase detector is always able to drive the phase locked loop into lock. A disadvantage of this approach is the production cost of tuning or trimming the VCO frequency range. For low cost, highly manufacturable products such an approach is not viable.
The second approach to avoid false locking is to train the phase locked loop using a phase/frequency detector that locks the phase locked loop to a clock (typically provided by a crystal oscillator) that is known to be very closely related to the frequency of the data stream to be recovered. To reduce costs, the reference crystal used is usually an integer submultiple of the data stream baud rate. For example, when recovering 155.56 MHz, a 19.44 MHz reference crystal can be used for training the phase locked loop (which is 1/8 the nominal frequency of the clock to be recovered).
A drawback of this second approach is that it only avoids false locking immediately subsequent to training. If it is ever possible to get into a false locked state at another time, there appears to be no way to detect this state and trigger retraining.
A typical case under which a phase locked loop may drift significantly from its nominal frequency is during a loss of signal event. For example, loss of signal occurs when a cable or fiber carrying the received data stream is cut. To detect loss of signal, many clock recovery phase locked loop circuits incorporate a counter that detects when no receive signal transitions occur over a significant number of bit intervals which form a loss of signal threshold. Upon detection of loss of signal, the phase locked loop may be forced to retrain to the reference.
There may also be transient disturbances on the receive signal path, however, that result in low transition density for a period of time sufficient to allow a phase locked loop to drift, while not violating a simple loss of signal threshold. To address this situation, many clock recovery phase locked loop circuits incorporate logic to monitor the received data stream and detect when unacceptably low transition density events occur and force retraining to the reference. For example, a clock recovery phase locked loop circuit could have logic that declares loss of signal after 80 bit intervals with no transitions and logic that declares low transition density if there are fewer than 8 transitions in a window of 240 bits, and triggers retraining if either event occurs.
While such a circuit may be fairly simple, it suffers from several drawbacks. Firstly, it may be difficult to prove that such an algorithm will detect all low transition density events that are capable of allowing the phase locked loop to drift sufficiently to lead to the false locking problem. Secondly, if a pessimistic algorithm is chosen so as to have higher confidence of detecting all problematic low transition density events, then the performance of the clock recovery phase locked loop will be downgraded by triggering retraining in many cases where retraining is unnecessary. This will result in a loss of synchronization to the received data stream which is typically plesiochronous to the reference.
This is particularly troublesome when dealing with SONET data streams or other data streams that are based on scrambled NRZ line coding. With such line coding the data stream appears much like a random bit stream with 50% average ones density having no limit on the run length of all zeros or all ones data, except that the longer the period without transitions in question, the less likely that it is to occur.
With such scrambled NRZ data, one is motivated to have optimistic loss of signal and low transition density detection algorithms (from the point of view of preventing the false locking problem) so as to not have these algorithms limiting the effective bit error rate performance of the system.
Fundamentally, with such attempts to detect problematic transition density events by examining the incoming data stream, one must implement very complex algorithms or accept significant degradation of the potential performance of the clock recovery phase locked loop in order to have high probability of avoiding the false locking problem.
Finally, there may be situations in which transient disturbances on the receive signal path result in high transition densities but nevertheless allow the clock recovery phase locked loop to drift sufficiently to allow false locking to occur. A typical scenario involves use of simple fiber optic receivers that are optimized for long reach. Such receivers of necessity incorporate automatic gain control so as to detect the lowest incoming light levels possible and may have no squelching circuitry so as to extract the maximum in low light level performance.
Under open fiber situations, however, such receive optics typically will generate essentially noise on their outputs, most likely at frequencies related to system noise on the power supply used by the optical receiver. When the output of such optics are fed to a clock recovery phase locked loop that depends on training to a reference as described, under an open fiber condition the phase locked loop may be driven significantly away from its nominal operating frequency with the result that it will not lock when a proper receive signal is restored, hence leading to the false locking problem.
A clock recovery phase locked loop sometimes reverts to an open loop mode, which is undesirable. Clock recovery is typically used at the receiving end of serial data links within systems. In order to minimize the number of circuits connected, high signal bit rates are typically used. In order to minimize cost, it is desirable to use VLSI device implementation technology of the minimum possible frequency capability that can achieve the required performance.
However, as mentioned earlier, when VCOs are implemented in VLSI devices and trimming is not used, such VCOs must have a wide frequency range to ensure that across variations in process, voltage and temperature, the VCO range always encompasses the frequency of data streams from which clock is to be recovered.
Further, in order to close the control loop around the clock recovery phase locked loop under all conditions, some logic circuitry, typically a divider, must operate at a frequency higher than the upper end of the VCO control range. This puts an onerous constraint on the design of phase locked loop control logic. For example, given typical VCO frequency ranges, when designing a 155 Mbit/s clock recovery circuit, the logic closing the loop must operate above 200 MHz. Similarly, the logic closing the loop for a 622 MHz clock recovery circuit must operate above 800 MHz.